An increasingly sought after approach for improving the performance of a metal oxide semiconductor field effect transistor (MOSFET), including a complimentary metal oxide semiconductor (CMOS) device is the introduction of strain induced band modification. Several approaches have been made to produce Strained Si-channel N and P MOSFETS with varying degrees of success.
One approach to producing a strained silicon channel, for example one in tensile strain, is by growing a thin silicon channel layer over step-graded SiGe. One implementation of a tensile strained Si channel is the growth of silicon over a relatively thick SiGe substrate. For example, most approaches for introducing strained silicon regions of the prior art employ complex multi-layer structures, for example relying on relatively thick SiGe buffer layers to achieve tensile stress in the surface silicon channel. Conventional processes such as ultra-high-vacuum chemical vapor deposition (UHV) and molecular Beam Epitaxy (MBE) are low-throughput processes which have been economically prohibitive in applying for high throughput CMOS manufacturing processes. In addition, although more complex devices, such as silicon-on-insulator (SOI) devices have incorporated strained silicon substrates, such devices require complex manufacturing processes which are cost prohibitive and generally incompatible with CMOS manufacturing technology.
In particular, it is important to achieve a low-defect density in the strained silicon layer used for forming the strained silicon channel in a CMOS device. For example, the epitaxially grown silicon layer must be grown a relatively defect-free surface avoiding nucleation of dislocations which can adversely degrade electrical properties. For example, nucleation of dislocations in the strained silicon layer due to propagating strain mismatches in the SiGe layer are undesirable and attempts have been made to reduce the propagation of dislocations by various methods.
Other difficulties related to growing low defect density strained silicon layers are related to the reaction kinetics of the deposition process to epitaxially grown silicon. For example, processes of the prior art have typically used silane and chlorosilane precursors to form epitaxial silicon and SiGe layers. The reaction temperatures typically have been carried out at temperatures greater than about 700° C. to achieve higher deposition rates and improve film uniformity by deposition in the mass transport limited regime. However, due to several factors including the undesirable effects of thermal gradients which contribute to dislocation nucleation, lower temperature epitaxial growth is frequently a preferred process. However, at lower deposition temperatures e.g., less than about 700° C., deposition rates for silane or chlorosilanes may be as low as 10 nanometers/minute requiring extended deposition times to form a multi-layer strained-Si channel device.
There is therefore a need in the semiconductor processing art to develop an improved processing method for forming strained silicon channel MOSFET devices to produce a low defect strained silicon channel with increased process wafer throughput.
It is therefore an object of the invention to provide an improved processing method for forming strained silicon channel MOSFET devices to produce a low defect density strained silicon channel with increased process wafer throughput while overcoming other shortcomings and deficiencies of the prior art.